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1 ltc2605/ltc2615/ltc2625 2605f octal 16-/14-/12-bit rail-to-rail dacs in 16-lead ssop the ltc ? 2605/ltc2615/ltc2625 are octal 16-, 14- and 12-bit, 2.7v to 5.5v rail-to-rail voltage-output dacs in 16-lead narrow ssop packages. they have built-in high performance output buffers and are guaranteed monotonic. these parts establish new board-density benchmarks for 16- and 14-bit dacs and advance performance standards for output drive, crosstalk and load regulation in single-supply, voltage-output multiples. the parts use the 2-wire i 2 c compatible serial interface. the ltc2605/ltc2615/ltc2625 operate in both the standard mode (maximum clock rate of 100khz) and the fast mode (maximum clock rate of 400khz). the ltc2605/ltc2615/ltc2625 incorporate a power-on reset circuit. during power-up, the voltage outputs rise less than 10mv above zero scale; and after power-up, they stay at zero scale until a valid write and update take place. the power-on reset circuit resets the ltc2605-1/ ltc2615-1/ltc2625-1 to midscale. the voltage output stays at midscale until a valid write and update takes place. smallest pin-compatible octal dacs: ltc2605: 16 bits ltc2615: 14 bits ltc2625: 12 bits guaranteed monotonic over temperature 400khz i 2 c interface wide 2.7v to 5.5v supply range low power operation: 250 a per dac at 3v individual channel power-down to 1 a, max ultralow crosstalk between dacs (<10 v) high rail-to-rail output drive ( 15ma, min) double-buffered digital inputs 27 selectable addresses ltc2605/ltc2615/ltc2625: power-on reset to zero scale ltc2605-1/ltc2615-1/ltc2625-1: power-on reset to midscale tiny 16-lead narrow ssop package mobile communications process control and industrial automation instrumentation automatic test equipment differential nonlinearity (ltc2605) applicatio s u features descriptio u block diagra w code 0 16384 32768 49152 65535 dnl (lsb) 2605 g02 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v 2 15 1 gnd v out a v out b v out c v out d ref ca2 scl v cc v out h v out g v out f v out e ca0 ca1 sda 2605/15/25 bd 16 dac a 3 14 4 13 5 7 6 8 10 11 9 12 2-wire interface 32-bit shift register register register dac h register register dac b register register dac g register register dac c register register dac f register register dac d register register dac e register register , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
2 ltc2605/ltc2615/ltc2625 2605f a u g w a w u w a r b s o lu t exi t i s order part number wu u package / o rder i for atio any pin to gnd ........................................... C 0.3v to 6v any pin to v cc .............................................C 6v to 0.3v maximum junction temperature .......................... 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 gnd v out a v out b v out c v out d gn package 16-lead plastic ssop ref ca2 scl v cc v out h v out g v out f v out e ca0 ca1 sda t jmax = 125 c, ja = 150 c/w ltc2605cgn LTC2605CGN-1 ltc2605ign ltc2605ign-1 ltc2615cgn ltc2615cgn-1 ltc2615ign ltc2615ign-1 ltc2625cgn ltc2625cgn-1 ltc2625ign ltc2625ign-1 consult ltc marketing for parts specified with wider operating temperature ranges. 2605 26051 2605i 26o5i1 2615 26151 2615i 2615i1 2625 26251 2625i 2625i1 (note 1) operating temperature range ltc2605c/ltc2615c/ltc2625c ............. 0 c to 70 c ltc2605c-1/ltc2615c-1/ltc2625c-1 ... 0 c to 70 c ltc2605i/ltc2615i/ltc2625i ............ C 40 c to 85 c ltc2605i-1/ltc2615i-1/ltc2625i-1 .. C 40 c to 85 c gn part marking e lectr ic al c c hara terist ics the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), v out unloaded, unless otherwise noted. ltc2625/-1 ltc2615/-1 ltc2605/-1 symbol parameter conditions min typ max min typ max min typ max units dc performance resolution 12 14 16 bits monotonicity (note 2) 12 14 16 bits dnl differential nonlinearity (note 2) 0.5 1 1lsb inl integral nonlinearity (note 2) 1 4 4 16 18 64 lsb load regulation v ref = v cc = 5v, midscale i out = 0ma to 15ma sourcing 0.02 0.125 0.07 0.5 0.3 2 lsb/ma i out = 0ma to 15ma sinking 0.03 0.125 0.10 0.5 0.4 2 lsb/ma v ref = v cc = 2.7v, midscale i out = 0ma to 7.5ma sourcing 0.04 0.25 0.15 1 0.6 4 lsb/ma i out = 0ma to 7.5ma sinking 0.07 0.25 0.20 1 0.8 4 lsb/ma zse zero-scale error code = 0 1.7 9 1.7 9 1.7 9 mv v os offset error (note 4) 1 9 1 9 1 9mv v os temperature 5 5 5 v/ c coefficient ge gain error 0.1 0.7 0.1 0.7 0.1 0.7 %fsr gain temperature 8 8 8 ppm/ c coefficient
3 ltc2605/ltc2615/ltc2625 2605f symbol parameter conditions min typ max units the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), v out unloaded, unless otherwise noted. (note 9) e lectr ic al c c hara terist ics psr power supply rejection v cc 10% C80 db r out dc output impedance v ref = v cc = 5v, midscale; C15ma i out 15ma 0.02 0.15 ? v ref = v cc = 2.7v, midscale; C7.5ma i out 7.5ma 0.03 0.15 ? dc crosstalk (note 10) due to full scale output change (note 11) 10 v due to load current change 3.5 v/ma due to powering down (per channel) 7 v i sc short-circuit output current v cc = 5.5v, v ref = 5.5v code: zero scale; forcing output to v cc 15 34 60 ma code: full scale; forcing output to gnd 15 34 60 ma v cc = 2.7v, v ref = 2.7v code: zero scale; forcing output to v cc 7.5 20 50 ma code: full scale; forcing output to gnd 7.5 27 50 ma reference input input voltage range 0v cc v resistance normal mode 11 16 20 k ? capacitance 90 pf i ref reference current, power down mode dac powered down 0.001 1 a power supply v cc positive supply voltage for specified performance 2.7 5.5 v i cc supply current v cc = 5v (note 3) 2.50 4.0 ma v cc = 3v (note 3) 2.00 3.2 ma dac powered down (note 3) v cc = 5v 0.38 1.0 a dac powered down (note 3) v cc = 3v 0.16 1.0 a digital i/o (note 9) v il low level input voltage 0.3v cc v (sda and scl) v ih high level input voltage 0.7v cc v (sda and scl) v il(ca) low level input voltage (ca0 to ca2) see test circuit 1 0.15v cc v v ih(ca) high level input voltage (ca0 to ca2) see test circuit 1 0.85v cc v r inh resistance from ca n (n = 0,1,2) see test circuit 2 10 k ? to v cc to set ca n = v cc r inl resistance from ca n (n = 0,1,2) see test circuit 2 10 k ? to gnd to set ca n = gnd r inf resistance from ca n (n = 0,1,2) see test circuit 2 2m ? to v cc or gnd to set ca n = float v ol low level output voltage sink current = 3ma 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , 20 + 0.1c b 250 ns c b = 10pf to 400pf (note 7) t sp pulse width of spikes surpassed 050ns by input filter i in input leakage 0.1v cc v in 0.9v cc 1 a c in i/o pin capacitance (note 12) 10 pf c b capacitance load for each bus line 400 pf c can external capacitive load on 10 pf address pins ca0, ca1 and ca2
4 ltc2605/ltc2615/ltc2625 2605f ti i g characteristics u w the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (see figure 1) (notes 8, 9) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: linearity and monotonicity are defined from code k l to code 2 n C 1, where n is the resolution and k l is given by k l = 0.016(2 n /v ref ), rounded to the nearest whole code. for v ref = 4.096v and n = 16, k l = 256 and linearity is defined from code 256 to code 65,535. note 3: sda, scl at 0v or v cc , ca0, ca1 and ca2 floating. note 4: inferred from measurement at code 256 (ltc2605/ltc2605-1), code 64 (ltc2615/ltc2615-1) or code 16 (ltc2625/ltc2625-1) and at full scale. note 5: v cc = 5v, v ref = 4.096v. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k ? in parallel with 200pf to gnd. note 6: v cc = 5v, v ref = 4.096v. dac is stepped 1lsb between half scale and half scale C 1. load is 2k ? in parallel with 200pf to gnd. note 7: c b = capacitance of one bus line in pf. note 8: all values refer to v ih(min) and v il(max) levels. note 9: these specifications apply to ltc2605/ltc2605-1, ltc2615/ ltc2615-1 and ltc2625/ltc2625-1. note 10: dc crosstalk is measured with v cc = 5v and v ref = 4096v, with the measured dac at midscale, unless otherwise noted. note 11: r l = 2k ? to gnd or v cc . note 12: guaranteed by design and not production tested. e lectr ic al c c hara terist ics the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), v out unloaded, unless otherwise noted. ltc2625/-1 ltc2615/-1 ltc2605/-1 symbol parameter conditions min typ max min typ max min typ max units ac performance t s settling time (note 5) 0.024% ( 1lsb at 12 bits) 7 7 7 s 0.006% ( 1lsb at 14 bits) 9 9 s 0.0015% ( 1lsb at 16 bits) 10 s settling time for 1lsb step 0.024% ( 1lsb at 12 bits) 2.7 2.7 2.7 s (note 6) 0.006% ( 1lsb at 14 bits) 4.8 4.8 s 0.0015% ( 1lsb at 16 bits) 5.2 s voltage output slew rate 0.80 0.80 0.80 v/ s capacitive load driving 1000 1000 1000 pf glitch impulse at midscale transition 12 12 12 nv ? s multiplying bandwidth 180 180 180 khz e n output voltage noise density at f = 1khz 120 120 120 nv/ hz at f = 10khz 100 100 100 nv/ hz output voltage noise 0.1hz to 10hz 15 15 15 v p-p symbol parameter conditions min typ max units v cc = 2.7v to 5.5v f scl scl clock frequency 0 400 khz t hd(sta) hold time (repeated) start condition 0.6 s t low low period of the scl clock pin 1.3 s t high high period of the scl clock pin 0.6 s t su(sta) set-up time for a repeated start program 0.6 s t hd(dat) data hold time 0 0.9 s t su(dat) data set-up time 100 ns t r rise time of both sda and scl signals (note 7) 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 7) 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition 0.6 s t buf bus free time between a stop and start condition 1.3 s
5 ltc2605/ltc2615/ltc2625 2605f typical perfor a ce characteristics uw ltc2605 integal nonlinearity (inl) v ih(ca n ) /v il(ca n ) ca n 100 ? 2605/15/25 ec01 e lectr ic al c c hara terist ics test circuit 1 test circuit 2 code 0 16384 32768 49152 65535 inl (lsb) 2605 g01 32 24 16 8 0 C8 C16 C24 C32 v cc = 5v v ref = 4.096v code 0 16384 32768 49152 65535 dnl (lsb) 2605 g02 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v temperature ( c) C50 C30 C10 10 30 50 70 90 inl (lsb) 2605 g03 32 24 16 8 0 C8 C16 C24 C32 v cc = 5v v ref = 4.096v inl (pos) inl (neg) temperature ( c) C50 C30 C10 10 30 50 70 90 dnl (lsb) 2605 g04 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v dnl (pos) dnl (neg) v ref (v) 0 1 2 3 4 5 inl (lsb) 2605 g05 32 24 16 8 0 C8 C16 C24 C32 v cc = 5.5v inl (pos) inl (neg) v ref (v) 0 1 2 3 4 5 dnl (lsb) 2605 g06 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 v cc = 5.5v dnl (pos) dnl (neg) differential nonlinearity (dnl) inl vs temperature dnl vs temperature inl vs v ref dnl vs v ref gnd r inh /r inl /r inf v dd 2605/15/25 ec02
6 ltc2605/ltc2615/ltc2625 2605f ltc2625 typical perfor a ce characteristics uw ltc2605 settling to 1lsb settling of full-scale step 5 s/div 2605 g08 v out 100 v/div scr 2v/div settling to 1lsb v cc = 5v, v ref = 4.096v code 512 to 65535 step average of 2048 events 12.3 s 9th clock of 3rd data byte ltc2615 integral nonlinearity (inl) differential nonlinearity (dnl) integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb settling to 1lsb code 0 4096 8192 12288 16383 inl (lsb) 2605 g09 8 6 4 2 0 C2 C4 C6 C8 v cc = 5v v ref = 4.096v code 0 4096 8192 12288 16383 dnl (lsb) 2605 g10 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v 2 s/div 2605 g11 v out 100 v/div scl 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 8.9 s 9th clock of 3rd data byte code 0 1024 2048 3072 4095 inl (lsb) 2605 g12 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 v cc = 5v v ref = 4.096v code 0 1024 2048 3072 4095 dnl (lsb) 2605 g13 v cc = 5v v ref = 4.096v 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 2 s/div 2605 g14 v out 1mv/div scl 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 6.8 s 9th clock of 3rd data byte 2 s/div 2605 g07 v out 100 v/div scl 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 9.7 s 9th clock of 3rd data byte
7 ltc2605/ltc2615/ltc2625 2605f typical perfor a ce characteristics uw ltc2605/ltc2615/ltc2625 current limiting gain error vs temperature offset error vs v cc zero-scale error vs temperature i cc shutdown vs v cc gain error vs v cc load regulation offset error vs temperature i out (ma) C40 C30 C20 C10 0 10 20 30 40 ? v out (v) 2605 g15 0.10 0.08 0.06 0.04 0.02 0 C0.02 C0.04 C0.06 C0.08 C0.10 v ref = v cc = 5v v ref = v cc = 3v v ref = v cc = 5v v ref = v cc = 3v code = midscale i out (ma) C35 C25 C15 C5 5 15 25 35 ? v out (mv) 2606 g16 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v ref = v cc = 5v code = midscale v ref = v cc = 3v temperature ( c) C50 C30 C10 10 30 50 70 90 offset error (mv) 2605 g17 3 2 1 0 C1 C2 C3 temperature ( c) C50 C30 C10 10 30 50 70 90 zero-scale error (mv) 2605 g18 3 2.5 2.0 1.5 1.0 0.5 0 temperature ( c) C50 C30 C10 10 30 50 70 90 gain error (%fsr) 2605 g19 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 offset error (mv) 2605 g20 3 2 1 0 C1 C2 C3 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 gain error (%fsr) 2605 g21 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 i cc (na) 2605 g22 450 400 350 300 250 200 150 100 50 0 large-signal response 2.5 s/div v out 0.5v/div 2605 g23 v ref = v cc = 5v 1/4-scale to 3/4-scale
8 ltc2605/ltc2615/ltc2625 2605f typical perfor a ce characteristics uw ltc2605/ltc2615/ltc2625 midscale glitch impulse power-on reset glitch headroom at rails vs output current v out 10mv/div scl 2v/div 2.5 s/div 2605 g24 transition from ms-1 to ms transition from ms to ms-1 9th clock of 3rd data byte v out 10mv/div 250 s/div 2605 g25 v cc 1v/div 4mv peak i out (ma) 0 1 2 3 4 5 6 7 8 910 v out (v) 2605 g26 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5v sourcing 3v sourcing 3v sinking 5v sinking power-on reset to midscale 1v/div 500 s/div 2605 g27 v cc v out v ref = v cc 2605 g28 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 012 logic voltage (v) i cc (ma) 345 v cc = 5v sweep scl and sda 0v to v cc and v cc to 0v supply current vs logic voltage multiplying bandwidth frequency (hz) 1k db 0 C3 C6 C9 C12 C15 C18 C21 C24 C27 C30 C33 C36 1m 2605 g29 10k 100k v cc = 5v v ref (dc) = 2v v ref (ac) = 0.2v p-p code = full scale short-circuit output current vs v out (sinking) short-circuit output current vs v out (sourcing) output voltage noise, 0.1hz to 10hz v out 10 v/div seconds 012345678910 2605 g30 5 4 3 2 1 0 10ma/div 0ma 10ma 20ma 30ma 40ma 1v/div 2605 g31 v cc = 5.5v v ref = 5.6v code = 0 v out swept 0v to v cc 0123 45 10ma/div 0ma C10ma C20ma C30ma C40ma C50ma 1v/div 2605 g32 v cc = 5.5v v ref = 5.6v code = full scale v out swept v cc to 0v
9 ltc2605/ltc2615/ltc2625 2605f block diagra w ti i g diagra u ww figure 1 2 15 1 gnd v out a v out b v out c v out d ref ca2 scl v cc v out h v out g v out f v out e ca0 ca1 sda 2605/15/25 bd01 16 dac a 3 14 4 13 5 7 6 8 10 11 9 12 2-wire interface 32-bit shift register dac register dac register dac register dac register dac register dac register dac register dac register input register input register input register input register input register input register input register input register dac h dac b dac g dac c dac f dac d dac e sda t f s t r t low t hd(sta) all voltage levels refer to v ih(min) and v il(max) levels t hd(dat) t su(dat) t su(sta) t hd(sta) t su(sto) t sp t buf t r t f t high scl s p s 2605/15/25 td01 pi n fu n ctio n s uuu gnd (pin 1): analog ground. v out a to v out h (pins 2-5 and 12-15): dac analog voltage output. the output range is 0v to v ref . ref (pin 6): reference voltage input. 0v v ref v cc . ca2 (pin 7): chip address bit 2. tie this pin to v cc , gnd or leave it floating to select an i 2 c slave address for the part (table 2). scl (pin 8): serial clock input pin. data is shifted into the sda pin at the rising edges of the clock. this high impedance pin requires a pull-up resistor or current source to v cc . sda (pin 9): serial data bidirectional pin. data is shifted into the sda pin and acknowledged by the sda pin. this is a high impedance pin while data is shifted in. it is an open- drain n-channel output during acknowledgment. this pin requires a pull-up resistor or current source to v cc . ca1 (pin 10): chip address bit 1. tie this pin to v cc , gnd or leave it floating to select an i 2 c slave address for the part (table 2). ca0 (pin 11): chip address bit 0. tie this pin to v cc , gnd or leave it floating to select an i 2 c slave address for the part (table 2). v cc (pin 16): supply voltage input. 2.7v v cc 5.5v.
10 ltc2605/ltc2615/ltc2625 2605f table 1. command* c3 c2 c1 c0 0000 w rite to input register n 0001 u pdate (power up) dac register n 0010 w rite to input register n, update (power up) all n 0011 w rite to and update (power up) n 0100 power down n 1111 no o peration *address and command codes not shown are reserved and should not be used. address (n)* a3 a2 a1 a0 0000 dac a 0001 dac b 0010 dac c 0011 dac d 0100 dac e 0101 dac f 0110 dac g 0111 dac h 1111 all dacs where k is the decimal equivalent of the binary dac input code, n is the resolution and v ref is the voltage at ref (pin 6). serial digital interface the ltc2605/ltc2615/ltc2625 communicate with a host using the standard 2-wire digital interface. the timing diagram (figure 1) shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the value of these pull-up resistors is dependent on the power supply and can be obtained from the i 2 c specifica- tions. for an i 2 c bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pf. the ltc2605/ltc2615/ltc2625 are receive-only (slave) devices. the master can write to the ltc2605/ltc2615/ ltc2625. the ltc2605/ltc2615/ltc2625 do not respond to a read from the master. the start (s) and stop (p) conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communica- tion to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. operatio u power-on reset the ltc2605/ltc2615/ltc2625 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. the ltc2605-1/ ltc2615-1/ltc2625-1 set the voltage outputs to midscale when power is first applied. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2605/ ltc2615/ltc2625 contain circuitry to reduce the power-on glitch: the analog outputs typically rise less than 10mv above zero scale during power on if the power supply is ramped to 5v in 1ms or more. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics section. power supply sequencing the voltage at ref (pin 6) should be kept within the range C 0.3v v ref v cc + 0.3v (see absolute maximum ratings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 16) is in transition. transfer function the digital-to-analog transfer function is v k v out ideal n ref () = ? ? ? ? ? ? 2
11 ltc2605/ltc2615/ltc2625 2605f operatio u acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge (active low) generated by the slave lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock pulse. the slave-receiver must pull down the sda during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. the ltc2605/ltc2615/ltc2625 respond to a write by a mas- ter in this manner. the ltc2605/ltc2615/ltc2625 do not acknowledge a read (it retains sda high during the period of the acknowledge clock pulse). chip address the state of ca0, ca1 and ca2 decides the slave address of the part. the pins ca0, ca1 and ca2 can be each set to any one of three states: v cc , gnd or float. this results in 27 selectable addresses for the part. the addresses corresponding to the states of ca0, ca1 and ca2 and the global address are shown in table 2. in addition to the address selected by the address pins, the parts also respond to a global address. this address allows a common write to all ltc2605, ltc2615 and ltc2625 parts to be accomplished with one 3-byte write transaction on the i 2 c bus. the global address is a 7-bit hardwired address and is not selectable by ca0, ca1 and ca2. the maximum capacitive load allowed on the address pins (ca0, ca1 and ca2) is 10pf. write word protocol the master initiates communication with the ltc2605/ ltc2615/ltc2625 with a start condition and a 7-bit slave address followed by the write bit (w) = 0. the ltc2605/ltc2615/ltc2625 acknowledges by pulling the sda pin low at the 9th clock if the 7-bit slave address matches the address of the parts (set by ca0, ca1 and ca2) or the global address. the master then transmits three bytes of data. the ltc2605/ltc2615/ltc2625 acknowledges each byte of data by pulling the sda line low at the 9th clock of each data byte transmission. after receiving three complete bytes of data, the ltc2605/ ltc2615/ltc2625 executes the command specified in the 24-bit input word. if more than three data bytes are transmitted after a valid 7-bit slave address, the ltc2605/ltc2615/ltc2625 do not acknowledge the extra bytes of data (sda is high during the 9th clock). the format of the three data bytes is shown in figure 2. the first byte of the input word consists of the 4-bit command and 4- bit dac address. the next two bytes consist of the 16-bit data word. the 16-bit data word consists of the 16-, 14- or 12-bit input code, msb to lsb, followed by 0, 2 or 4 dont care bits (ltc2605, ltc2615 and ltc2625 respectively). a typical i 2 c write transaction is shown in figure 3. s input word write word protocol for ltc2605/ltc2615/ltc2625 input word (ltc2605) slave address w a a 1st data byte 2nd data byte a 3rd data byte ap 2605/2615/2625 o01 1st data byte 2nd data byte 3rd data byte 1st data byte 2nd data byte 3rd data byte 1st data byte 2nd data byte 3rd data byte c3 c2 c1 c0 a3 a2 a1 a0 d13 d14 d15 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 input word (ltc2615) c3 c2 c1 c0 a3 a2 a1 a0 d11 d12 d13 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x input word (ltc2625) c3 c2 c1 c0 a3 a2 a1 a0 d9 d10 d11 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x figure 2
12 ltc2605/ltc2615/ltc2625 2605f the command (c3-c0) and address (a3-a0) assignments are shown in table 1. the first four commands in the table consist of write and update operations. a write operation loads the 16-bit data word from the 32-bit shift register into the input register of the selected dac, n. an update operation copies the data word from the input register to the dac register. once copied into the dac register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the dac output. the update operation also powers up the selected dac if it had been in power-down mode. the data path and registers are shown in the block diagram. table 2. slave address map ca2 ca1 ca0 sa6 sa5 sa4 sa3 sa2 sa1 sa0 gndgndgnd0010000 gnd gnd float 0010001 gnd gnd v cc 0010010 gnd float gnd 0010011 gnd float float 0100000 gnd float v cc 0100001 gnd v cc gnd0100010 gnd v cc float 0100011 gnd v cc v cc 0110000 float gnd gnd 0110001 float gnd float 0110010 float gnd v cc 0110011 float float gnd 1000000 float float float 1000001 float float v cc 1000010 float v cc gnd1000011 float v cc float 1010000 float v cc v cc 1010001 v cc gndgnd1010010 v cc gnd float 1010011 v cc gnd v cc 1100000 v cc float gnd 1100001 v cc float float 1100010 v cc float v cc 1100011 v cc v cc gnd1110000 v cc v cc float 1110001 v cc v cc v cc 1110010 global address 1110011 power down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight outputs are needed. when in power-down, the buffer amplifiers and reference inputs are disabled and draw essentially zero current. the dac outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 90k resistors. when all eight dacs are powered down, the bias generation circuit is also disabled. input- and dac- registers are not disturbed during power-down. any channel or combination of channels can be put into power-down mode by using command 0100 b in combination with the appropriate dac address, (n). the 16-bit data word is ignored. the supply and reference currents are reduced by approximately 1/8 for each dac powered down; the effective resistance at ref (pin 6) rises accordingly, becoming a high-impedance input (typically >1g ? ) when all eight dacs are powered down. normal operation can be resumed by executing any com- mand which includes a dac update, as shown in table 1. the selected dac is powered up as its voltage output is updated. there is an initial delay as the dac powers up before it begins its usual settling behavior. if less than eight dacs are in a powered-down state prior to the updated command, the power-up delay is 5 s. if, on the other hand, all eight dacs are powered down, then the bias generation circuit is also disabled and must be restarted. in this case, the power-up delay is greater: 12 s for v cc = 5v, 30 s for v cc = 3v. voltage outputs each of the eight rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the amplifiers ability to maintain the rated voltage accuracy over a wide range of load conditions. the measured change in output voltage per milliampere of forced load current change is expressed in lsb/ma. operatio u
13 ltc2605/ltc2615/ltc2625 2605f dc output impedance is equivalent to load regulation and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the amplifiers dc output impedance is 0.020 ? when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 ? typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 30 ? ? 1ma = 30mv. see the graph headroom at rails vs output current in the typical performance characteristics section. the amplifiers are stable driving capacitive loads of up to 1000pf. board layout the excellent load regulation and dc crosstalk perfor- mance of these devices is achieved in part by keeping signal and power grounds separated internally and by reducing shared internal resistance to just 0.005 ? . the gnd pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. operatio u digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the devices ground pin as possible. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continu- ous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin of the part should be connected to analog ground. resistance from the gnd pin to system star ground should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.020 ? ), and will degrade dc crosstalk. note that the ltc2605/ltc2615/ltc2625 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in figure 4b. similarly, limiting can occur near full scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 4c. no full-scale limiting can occur if v ref is less than v cc C fse. offset and linearity are defined and tested over the region of the dac transfer function where no output limiting can occur.
14 ltc2605/ltc2615/ltc2625 2605f operatio u figure 3. typical ltc2605 input waveform?rogramming dac output for full scale ack ack 123456789123456789123456789123456789 2605/15/25 o02 ack start stop full-scale voltage zero-scale voltage sda sa6 sa5 sa4 sa3 sa2 sa1 sa0 scl v out c2 c3 c3 c2 c1 c0 a3 a2 a1 a0 c1 c0 a3 a2 a1 a0 ack command d15 d14 d13 d12 d11 d10 d9 d8 ms data d7 d6 d5 d4 d3 d2 d1 d0 ls data sa6 sa5 sa4 sa3 sa2 sa1 sa0 wr slave address
15 ltc2605/ltc2615/ltc2625 2605f u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) figure 4. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function, (b) effect of negative offset for codes near zero scale, (c) effect of positive full-scale error for codes near full scale operatio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 2605/15/25 o05 input code (b) output voltage negative offset 0v 32, 768 0 65, 535 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
16 ltc2605/ltc2615/ltc2625 2605f part number description comments ltc1458/ltc1458l quad 12-bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.096v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1654 dual 14-bit rail-to-rail v out dac programmable speed/power, 3.5 s/750 a, 8 s/450 a ltc1655/ltc1655l single 16-bit v out dac with serial interface in so-8 v cc = 5v(3v), low power, deglitched ltc1657/ltc1657l parrallel 5v/3v 16-bit v out dac low power, deglitched, rail-to-rail v out ltc1660/ltc1665 octal 10-/8-bit v out dac in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1821 parallel 16-bit voltage output dac precision 16-bit settling in 2 s for 10v step ltc2600/ltc2610/ octal 16-/14-/12-bit v out dacs in 16-lead ssop 250 a per dac, 2.5vC5.5v supply range, rail-to-rail ltc2620 output, spi interface ltc2601/ltc2611/ single 16-/14-/12-bit v out dacs in 10-lead dfn 300 a per dac, 2.5vC5.5v supply range, rail-to-rail ltc2621 output, spi interface ltc2602/ltc2612/ dual 16-/14-/12-bit v out dacs in 8-lead msop 300 a per dac, 2.5vC5.5v supply range, rail-to-rail ltc2622 output, spi interface ltc2604/ltc2614/ quad 16-/14-/12-bit v out dacs in 16-lead ssop 250 a per dac, 2.5vC5.5v supply range, rail-to-rail ltc2624 output, spi interface ltc2606/ltc2616/ single 16-/14-/12-bit v out dacs with i 2 c interface in 10-lead dfn 270 a per dac, 2.7vC5.5v supply range, rail-to-rail ltc2626 output, i 2 c interface ? linear technology corporation 2005 lt/lwi/tp 0405 500 ?printed in the usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts typical applicatio u disable adc 4.096v 5v 10k 10k cs sck spi bus v cc v in v cc v cc v ref v ref 5v r6 7.5k r5 dac outputs 7.5k c10 100pf r8 22 tp4 dac b u5 lt1461acs8-4 2 4 6 3 v in gnd v out shdn tp5 dac c tp6 dac d tp7 dac e u3 ltc2428cg 13 12 1 5 6 7 8 9 10 15 4 3 2 11 14 17 18 19 20 21 22 23 24 25 26 2605 ta01 27 28 16 ch4 ch3 gnd zs set fs set gnd muxout ch0 ch1 ch6 adcin v cc v cc v cc v ref v cc ch2 ch5 ch7 gnd clk csmux d in gnd csadc sd0 sck fo gnd gnd gnd jp1 on/off c1 0.1 f c2 0.1 f c5 0.1 f c4 0.1 f tp8 dac f tp9 dac g tp3 dac a jp2 v ref tp10 dac h u2 ltc2605cgn i 2 c bus 13 12 5 6 1 15 16 4 3 2 11 10 7 9 8 14 v out f v out e gnd v out d ref sda scl v out h v cc v out c v out b v out a ca2 ca1 ca0 v out g 4-/8-channel mux 3 1 2 v cc address selection v cc r7 7.5k 20-bit adc + C 3 1 2 tp13 gnd tp11 v ref c8 1 f 16v c9 0.1 f u4 lt1236acs8-5 2 4 6 v in gnd v out c6 0.1 f c7 4.7 f 6.3v regulator 5v ref v cc jp3 v cc 3 1 2 tp12 v cc demonstration circuit?tc2428 20-bit adc measures key performance parameters

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